1. Field of the Invention
The invention relates to a fabricating method of a transistor structure. More particularly, the invention relates to a fabricating method of a vertical transistor and a vertical transistor array.
2. Description of Related Art
As sizes of devices are gradually decreased, to satisfy different applications of integrated circuits, a transistor pattern of a current semiconductor device is developed from a planar gate structure to a vertical gate structure.
However, a great problem of the semiconductor device of general vertical surrounding gate structure is the generation of floating body effect, especially when gate length thereof is greater than 40 nanometers. Wherein, the so-called floating body effect refers that in the semiconductor device, charges are accumulated in a channel, and if the charges are accumulated to certain degree, not only threshold voltage of the device is influenced, but also a current of drain area is suddenly increased. Moreover, the floating body effect may cause problem that device turns on automatically even no any voltage is exerted. Accordingly, reliability and stability of the device are influenced and current leakage is occurred.